A restricted dynamically reconfigurable architecture for low power processors.
Takeshi HiraoDahoo KimItaru HidaTetsuya AsaiMasato MotomuraPublished in: ReConFig (2013)
Keyphrases
- low power
- reconfigurable architecture
- signal processor
- low cost
- power consumption
- high speed
- systolic array
- single chip
- parallel architecture
- parallel algorithm
- wireless transmission
- high power
- vlsi architecture
- parallel processing
- vlsi circuits
- logic circuits
- low power consumption
- power reduction
- cmos technology
- digital signal processing
- delay insensitive
- real time
- image sensor
- signal processing