Hiroshi Sasaki

Publication Activity (10 Years)

Years Active: 2005-2021
Publications (10 Years): 15

Top Topics

Energy Efficient

Top Venues

IEEE Comput. Archit. Lett.

IEICE Trans. Inf. Syst.

Publications

Keisuke Nishimura, Takahiro Ishikawa, Hiroshi Sasaki, Shinpei Kato
RAPLET: Demystifying Publish/Subscribe Latency for ROS Applications. RTCSA (2021)
Hiroshi Sasaki, Miguel A. Arroyo, M. Tarek Ibn Ziad, Koustubha Bhat, Kanad Sinha, Simha Sethumadhavan
Practical Byte-Granular Memory Blacklisting using Califorms. MICRO (2019)
Hiroshi Sasaki, Miguel A. Arroyo, M. Tarek Ibn Ziad, Koustubha Bhat, Kanad Sinha, Simha Sethumadhavan
Practical Byte-Granular Memory Blacklisting using Califorms. CoRR (2019)
Aaron Smith, Chris Fensch, Hiroshi Sasaki
Advances in Heterogeneous Computing from Hardware to Software (NII Shonan Meeting 2018-11). NII Shonan Meet. Rep. 2018 (2018)
Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa
Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs. IEICE Trans. Inf. Syst. (9) (2018)
Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan
Why do programs have heavy tails? IISWC (2017)
Hiroshi Sasaki, Alper Buyuktosunoglu, Augusto Vega, Pradip Bose
Mitigating Power Contention: A Scheduling Based Approach. IEEE Comput. Archit. Lett. 16 (1) (2017)
Teruo Tanimoto, Takatsugu Ono, Koji Inoue, Hiroshi Sasaki
Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors. IEEE Comput. Archit. Lett. 16 (2) (2017)
Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan
Heavy Tails in Program Structure. IEEE Comput. Archit. Lett. 16 (1) (2017)
Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro
A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform. MCSoC (2016)
Hiroshi Sasaki, Alper Buyuktosunoglu, Augusto Vega, Pradip Bose
Characterization and mitigation of power contention across multiprogrammed workloads. IISWC (2016)
Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa
Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping. HPGDMP@SC (2016)
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. (12) (2016)
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD (2015)
Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue
A flexible hardware barrier mechanism for many-core processors. ASP-DAC (2015)
Satoshi Imamura, Hiroshi Sasaki, Koji Inoue, Dimitrios S. Nikolopoulos
Power-capped DVFS and thread allocation with ANN models on modern NUMA systems. ICCD (2014)
Yuki Abe, Hiroshi Sasaki, Shinpei Kato, Koji Inoue, Masato Edahiro, Martin Peres
Power and Performance Characterization and Modeling of GPU-Accelerated Systems. IPDPS (2014)
Yuki Abe, Hiroshi Sasaki, Shinpei Kato, Koji Inoue, Masato Edahiro, Martin Peres
Power and performance of GPU-accelerated systems: A closer look. IISWC (2013)
Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
Predict-More Router: A Low Latency NoC Router with More Route Predictions. IPDPS Workshops (2013)
Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
McRouter: Multicast within a router for high performance network-on-chips. PACT (2013)
Keitarou Oka, Hiroshi Sasaki, Koji Inoue
Line sharing cache: Exploring cache capacity with frequent line value locality. ASP-DAC (2013)
Masaaki Kondo, Son Truong Nguyen, Tomoya Hirao, Takeshi Soga, Hiroshi Sasaki, Koji Inoue
SMYLEref: A reference architecture for manycore-processor SoCs. ASP-DAC (2013)
Hiroshi Sasaki, Satoshi Imamura, Koji Inoue
Coordinated power-performance optimization in manycores. PACT (2013)
Yuki Abe, Hiroshi Sasaki, Martin Peres, Koji Inoue, Kazuaki J. Murakami, Shinpei Kato
Power and Performance Analysis of GPU-Accelerated Systems. HotPower (2012)
Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura
Adaptive Data Compression on 3D Network-on-Chips. Inf. Media Technol. 7 (1) (2012)
Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura
Scalability-based manycore partitioning. PACT (2012)
Takaaki Hanada, Hiroshi Sasaki, Koji Inoue, Kazuaki J. Murakami
Performance evaluation of 3D stacked multi-core processors with temperature consideration. 3DIC (2011)
Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Cooperative shared resource access control for low-power chip multiprocessors. ISLPED (2009)
Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. IEEE Trans. Very Large Scale Integr. Syst. 17 (6) (2009)
Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, Hiroshi Nakamura
Power-performance modeling of heterogeneous cluster-based web servers. GRID (2009)
Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura
An intra-task dvfs technique based on statistical analysis of hardware events. Conf. Computing Frontiers (2007)
Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. SIGARCH Comput. Archit. News 35 (1) (2007)
Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Energy-efficient dynamic instruction scheduling logic through instruction grouping. ISLPED (2006)
Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Dynamic Instruction Cascading on GALS Microprocessors. PATMOS (2005)