A flexible hardware barrier mechanism for many-core processors.
Takeshi SogaHiroshi SasakiTomoya HiraoMasaaki KondoKoji InouePublished in: ASP-DAC (2015)
Keyphrases
- high end
- low cost
- parallel algorithm
- parallel processing
- hardware implementation
- parallel computation
- real time
- digital computer
- parallel processors
- outer sheath
- processing elements
- selection mechanism
- lightweight
- massively parallel
- computational power
- signal processor
- memory subsystem
- embedded processors
- parallel architectures
- multiprocessor systems
- multi core processors
- image processing
- general purpose processors
- signal processing
- single processor
- computer systems
- parallel architecture
- computational model
- hardware and software
- computing systems
- computing power