Evaluating architecture-level optimization in packet processing caches.

Kyosuke Tanaka Hayato Yamaki Shinobu Miwa Hiroki Honda

Published in: Comput. Networks (2020)

Keyphrases

real time
optimization algorithm
distributed processing
neural network
optimization problems
packet switching
management system
data processing
software architecture
parallel architecture
higher level
constrained optimization
application level
information processing
network architecture
processing elements