Towards Reconfigurable Cache Memory for a Multithreaded Processor.
Yoshiyasu OgasawaraIppei TateSatoshi WatanabeMikiko SatoKoichi SasadaKaname UchikuraKazunari AsanoMitaro NamikiHironori NakajoPublished in: PDPTA (2006)
Keyphrases
- multithreading
- memory hierarchy
- memory subsystem
- cache misses
- memory access
- computational power
- processor core
- parallel computing
- highly efficient
- shared memory multiprocessors
- shared memory
- memory management
- distributed memory
- memory bandwidth
- database workloads
- multi core processors
- low cost
- main memory
- memory efficient
- parallel programming
- computing power
- shared memory multiprocessor
- instruction set
- secondary storage
- multiprocessor systems
- computation intensive
- cache conscious
- massively parallel
- hardware implementation
- operating system
- parallel processing
- data access
- level parallelism
- systolic array
- high speed
- embedded processors
- parallel architectures
- external memory
- computer architecture
- field programmable gate array