Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.
Hironori NakajoMasanori YamatoShoji KawaharaNorito KatoKoichi SasadaMikiko SatoMitaro NamikiPublished in: PDPTA (2003)
Keyphrases
- multithreading
- multi threaded
- cache misses
- computational power
- multi core processors
- memory requirements
- highly efficient
- memory subsystem
- processor core
- parallel computing
- computational complexity
- distributed memory
- random access memory
- memory access
- data partitioning
- real time
- computer architecture
- response time
- general purpose
- social networks