Noboru Tanabe

Publication Activity (10 Years)

Years Active: 1989-2018
Publications (10 Years): 2

Top Topics

Top Venues

IEICE Trans. Inf. Syst.

Publications

Noboru Tanabe, Toshio Endo
Exhaustive evaluation of memory-latency sensitivity on manycore processors with large cache. HP3C (2018)
Noboru Tanabe, Toshio Endo
Characterizing Memory-Latency Sensitivity of Sparse Matrix Kernels. PDP (2018)
Noboru Tanabe, Atsushi Ohta
Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism. IEICE Trans. Inf. Syst. (12) (2013)
Noboru Tanabe, Sonoko Tomimori, Masami Takata, Kazuki Joe
Character of Graph Analysis Workloads and Recommended Solutions on Future Parallel Systems. ICA3PP (1) (2013)
Noboru Tanabe, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe
A memory accelerator with gather functions for bandwidth-bound irregular applications. IA3@SC (2011)
Noboru Tanabe, Yuuka Ogawa, Masami Takata, Kazuki Joe
Scaleable Sparse Matrix-Vector Multiplication with Functional Memory and GPUs. PDP (2011)
Noboru Tanabe, Hironori Nakajo
Acceleration for MPI derived datatypes using an enhancer of memory and network. IPDPS Workshops (2010)
Noboru Tanabe, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo
An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing. J. Supercomput. 51 (3) (2010)
Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe
The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. PDPTA (2009)
Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo
Network Interface Architecture for Scalable Message Queue Processing. ICPADS (2009)
Noboru Tanabe, Hironori Nakajo
Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. PVM/MPI (2008)
Noboru Tanabe, Hironori Nakajo
An Enhancer of Memory and Network for Cluster and its Applications. PDCAT (2008)
Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks (2007)
Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA (2007)
Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. IEEE Trans. Parallel Distributed Syst. 18 (9) (2007)
Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki
Implementation of PC Cluster System with Memory Mapped File by Commodity OS. PDPTA (2006)
Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe
DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. FPL (2006)
Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. ISHPC (2005)
Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT (2005)
Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA (2005)
Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano
A New Memory Module for Memory Intensive Applications. PARELEC (2004)
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Clust. Comput. 5 (1) (2002)
Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC (2002)
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
MEMOnet : Network interface plugged into a memory slot. CLUSTER (2000)
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN (2000)
Yasushi Kawakura, Noboru Tanabe, Shigeru Oyanagi
Improving the performance of global communication on a three-dimensional torus network. Systems and Computers in Japan 27 (6) (1996)
Noboru Tanabe, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi
Implementation of the prodigy parallel AI machine and performance evaluation of communication. Systems and Computers in Japan 23 (8) (1992)
Noboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi
Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY. ICPP (1) (1991)
Takashi Suzuoka, Noboru Tanabe, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi
Network Performance of the Prodigy Parallel AI Machine. Systems and Computers in Japan 20 (9) (1989)