Shigeru Oyanagi

Publication Activity (10 Years)

Years Active: 1977-2018
Publications (10 Years): 2

Top Topics

Top Venues

Int. J. Artif. Intell. Tools

Publications

Lin Meng, Takuma Hirayama, Shigeru Oyanagi
Underwater-Drone With Panoramic Camera for Automatic Fish Recognition Based on Deep Learning. IEEE Access 6 (2018)
Lin Meng, Takuma Hirayama, Shigeru Oyanagi
The Development of Underwater-Drone equipped with 360-degree Panorama Camera in Opensource Hardware. IIKI (2017)
Ryohei Ebina, Kenji Nakamura, Shigeru Oyanagi
A Real-Time Burst Analysis Method. Int. J. Artif. Intell. Tools 22 (5) (2013)
Truong Vinh Truong Duy, Katsuhiro Yamazaki, Kosai Ikegami, Shigeru Oyanagi
Hybrid MPI-OpenMP Paradigm on SMP Clusters: MPEG-2 Encoder and N-Body Simulation CoRR (2012)
Truong Vinh Truong Duy, Katsuhiro Yamazaki, Shigeru Oyanagi
Performance Evaluation of Treecode Algorithm for N-Body Simulation Using GridRPC System CoRR (2012)
Chu Van Thiem, Shigeru Oyanagi
An Input Buffer Architecture for On-chip Routers. ICNC (2011)
Ryohei Ebina, Kenji Nakamura, Shigeru Oyanagi
A Real-Time Burst Detection Method. ICTAI (2011)
Son Truong Nguyen, Shigeru Oyanagi
An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation. ARCS (2011)
Lin Meng, Shigeru Oyanagi
Control Independence Using Dual Renaming. ICNC (2010)
Son Truong Nguyen, Shigeru Oyanagi
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks. DSD (2010)
Son Truong Nguyen, Shigeru Oyanagi
The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers. ICNC (2010)
Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi
Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate. IEICE Trans. Inf. Syst. (10) (2009)
Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi
Three-stage pipeline implementation for SHA2 using data forwarding. FPL (2008)
Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi
Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding. FCCM (2008)
Tran Minh Quang, Shigeru Oyanagi, Katsuhiro Yamazaki
ExMiner: An Efficient Algorithm for Mining Top-K Frequent Patterns. ADMA (2006)
Tran Minh Quang, Shigeru Oyanagi, Katsuhiro Yamazaki
Mining the K-Most Interesting Frequent Patterns Sequentially. IDEAL (2006)
Tran Cong So, Shigeru Oyanagi, Katsuhiro Yamazaki
Speculative Selection Routing in 2D Torus Network. IEICE Trans. Inf. Syst. (7) (2004)
Shigeru Oyanagi, Kazuto Kubota, Akihiko Nakase
Mining WWW Access Sequence by Matrix Clustering. WEBKDD (2002)
Kazuto Kubota, Akihiko Nakase, Shigeru Oyanagi
Implementation and performance evaluation of dynamic scheduling for parallel decision tree generation. IPDPS (2001)
Yasushi Kawakura, Noboru Tanabe, Shigeru Oyanagi
Improving the performance of global communication on a three-dimensional torus network. Systems and Computers in Japan 27 (6) (1996)
Yasushi Kawakura, Shigeru Oyanagi
Improving the Performance of Global Communication on a 3D torus network. ICPP (3) (1994)
Noboru Tanabe, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi
Implementation of the prodigy parallel AI machine and performance evaluation of communication. Systems and Computers in Japan 23 (8) (1992)
Noboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi
Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY. ICPP (1) (1991)
Takashi Suzuoka, Noboru Tanabe, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi
Network Performance of the Prodigy Parallel AI Machine. Systems and Computers in Japan 20 (9) (1989)
Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama
A Dynamically Microprogammable Computer with Low-Level Parallelism. IEEE Trans. Computers 29 (7) (1980)
Shinji Tomita, Kiyoshi Shibayama, Shigeru Oyanagi, Hiroshi Hagiwara
Hardware Organization of a Low Level Parallel Processor. IFIP Congress (1977)