Hideki Ando

Publication Activity (10 Years)

Years Active: 1993-2022
Publications (10 Years): 11

Top Topics

Wireless Sensor

Energy Efficiency

Top Venues

IEICE Trans. Inf. Syst.

Publications

Hideki Ando
Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area. ICCD (2022)
Yasutaka Matsuda, Ryota Shioya, Hideki Ando
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison. IEICE Trans. Inf. Syst. (2) (2022)
Hideki Ando
SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue. MICRO (2019)
Reoma Matsuo, Ryota Shioya, Hideki Ando
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. IEEE Comput. Archit. Lett. 18 (2) (2019)
Keita Doi, Ryota Shioya, Hideki Ando
Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications. J. Inf. Process. 26 (2018)
Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando
Rearranging Random Issue Queue with High IPC and Short Delay. ICCD (2018)
Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. ARCS (2018)
Hideki Ando
Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices. MICRO (2018)
Ryota Shioya, Hideki Ando
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency. IEICE Trans. Inf. Syst. (3) (2016)
Hideki Ando, Ryota Shioya
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control. IEICE Trans. Inf. Syst. (2) (2016)
Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando
FXA: Executing Instructions in Front-End for Energy Efficiency. IEICE Trans. Inf. Syst. (4) (2016)
Ryota Shioya, Masahiro Goshima, Hideki Ando
A Front-End Execution Architecture for High Energy Efficiency. MICRO (2014)
Ryota Shioya, Hideki Ando
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. ICCD (2014)
Yuya Kora, Kyohei Yamaguchi, Hideki Ando
MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism. IEICE Trans. Inf. Syst. (12) (2014)
Yuya Kora, Kyohei Yamaguchi, Hideki Ando
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP. MICRO (2013)
Kyohei Yamaguchi, Yuya Kora, Hideki Ando
Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification. IEICE Trans. Inf. Syst. (9) (2012)
Kyohei Yamaguchi, Yuya Kora, Hideki Ando
Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path. ICCD (2011)
Yusuke Tanaka, Hideki Ando
Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction. IEICE Trans. Inf. Syst. (12) (2010)
Yusuke Tanaka, Hideki Ando
Reducing register file size through instruction pre-execution enhanced by value prediction. ICCD (2009)
Kazunaga Hyodo, Kengo Iwamoto, Hideki Ando
Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation. IEICE Trans. Inf. Syst. (11) (2009)
Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada
Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation. Inf. Media Technol. 3 (4) (2008)
Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada
Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation. MEDEA@PACT (2007)
Akio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada
Limits of Thread-Level Parallelism in Non-numerical Programs. Inf. Media Technol. 1 (2) (2006)
Hajime Shimada, Hideki Ando, Toshio Shimada
Pipeline stage unification: a low-energy consumption technique for future mobile processors. ISLPED (2003)
Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada
A preactivating mechanism for a VT-CMOS cache using address prediction. ISLPED (2002)
Hideki Ando, Yoshinobu Oasa, Ichiro Suzuki, Masafumi Yamashita
Distributed memoryless point convergence algorithm for mobile robots with limited visibility. IEEE Trans. Robotics Autom. 15 (5) (1999)
Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata
An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. EUROMICRO (1999)
Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya
Software pipelining with path selection. Systems and Computers in Japan 29 (9) (1998)
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya
Performance Comparison of ILP Machines with Cycle Time Evaluation. ISCA (1996)
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya
Unconstrained Speculative Execution with Predicated State Buffering. ISCA (1995)
Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya
Code scheduling on a superscalar processor: SARCH. Systems and Computers in Japan 26 (9) (1995)
Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. ICCD (1993)