Chikako Nakanishi

Publication Activity (10 Years)

Years Active: 1993-2018
Publications (10 Years): 3

Top Topics

Object Recognition

Vlsi Architecture

Top Venues

IEICE Electron. Express

Publications

Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]. IEICE Electron. Express 15 (12) (2018)
Yuri Nishizumi, Go Matsukawa, Koichi Kajihara, Taisuke Kodama, Shintaro Izumi, Hiroshi Kawaguchi, Chikako Nakanishi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature. SiPS (2017)
Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video. IEICE Electron. Express 14 (15) (2017)
Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya
Software pipelining with path selection. Systems and Computers in Japan 29 (9) (1998)
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya
Performance Comparison of ILP Machines with Cycle Time Evaluation. ISCA (1996)
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya
Unconstrained Speculative Execution with Predicated State Buffering. ISCA (1995)
Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya
Code scheduling on a superscalar processor: SARCH. Systems and Computers in Japan 26 (9) (1995)
Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. ICCD (1993)