Code scheduling on a superscalar processor: SARCH.
Chikako NakanishiHideki AndoHirohisa MachidaMasao NakayaPublished in: Systems and Computers in Japan (1995)
Keyphrases
- instruction scheduling
- multithreading
- instruction set
- computer architecture
- parallel processors
- multiprocessor systems
- scheduling problem
- processor core
- round robin
- parallel processing
- instruction set architecture
- highly efficient
- industry standard
- computational power
- precedence constraints
- high speed
- source code
- resource constraints
- scheduling algorithm
- error detection
- floating point
- highly parallel
- dynamic scheduling
- application specific
- real time
- fine grained
- flexible manufacturing systems
- general purpose
- binary codes
- windows xp
- code generation
- static analysis
- operating system
- web services