Toshio Shimada

Publication Activity (10 Years)

Years Active: 1983-2008
Publications (10 Years): 0

Publications

Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada
Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation. Inf. Media Technol. 3 (4) (2008)
Hideki Oshima, Ryotaro Kobayashi, Kazuki Shimura, Toshio Shimada
Power consumption reduction scheme focusing on the Depth of Speculative Execution. CIT (2008)
Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada
Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation. MEDEA@PACT (2007)
Akio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada
Limits of Thread-Level Parallelism in Non-numerical Programs. Inf. Media Technol. 1 (2) (2006)
Hajime Shimada, Hideki Ando, Toshio Shimada
Pipeline stage unification: a low-energy consumption technique for future mobile processors. ISLPED (2003)
Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada
A preactivating mechanism for a VT-CMOS cache using address prediction. ISLPED (2002)
Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata
An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. EUROMICRO (1999)
Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. IEEE J. Solid State Circuits 34 (11) (1999)
Kenji Nishida, Kenji Toda, Toshio Shimada, Yoshinori Yamaguchi
The Hardware Architecture of the CODA Real-Time Parallel Processor. PARCO (1993)
Kei Hiraki, Toshio Shimada, Satoshi Sekiguchi
Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor. International Conference on Supercomputing (1993)
Kenji Toda, Kenji Nishida, Shuichi Sakai, Toshio Shimada
A priority forwarding scheme for real-time multistage interconnection networks. RTSS (1992)
Toshio Shimada, Kenji Toda, Kenji Nishida
Real-Time Parallel Architecture for Sensor Funsion. J. Parallel Distributed Comput. 15 (2) (1992)
Kenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism. IPPS (1991)
Satoshi Sekiguchi, Toshio Shimada, Kei Hiraki
Sequential description and parallel execution language DFCII dataflow supercomputers. ICS (1991)
Toshitsugu Yuba, Toshio Shimada, Yoshinori Yamaguchi, Kei Hiraki, Shuichi Sakai
Dataflow computer development in Japan. ICS (1990)
Toshio Shimada, Satoshi Sekiguchi, Kei Hiraki
Data flow language DFC: Design and implementation. Systems and Computers in Japan 20 (6) (1989)
Kei Hiraki, Satoshi Sekiguchi, Toshio Shimada
Efficient vector processing on dataflow supercomputer SIGMA-1. SC (1988)
Kei Hiraki, Satoshi Sekiguchi, Toshio Shimada
Load scheduling schemes using inter - PE network. Systems and Computers in Japan 18 (1) (1987)
Toshitsugu Yuba, Kei Hiraki, Toshio Shimada, Satoshi Sekiguchi, Kenji Nishida
The SIGMA-1 dataflow computer. FJCC (1987)
Kei Hiraki, Kenji Nishida, Satoshi Sekiguchi, Toshio Shimada
Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of Processors. ICPP (1986)
Toshio Shimada, Kei Hiraki, Kenji Nishida, Satoshi Sekiguchi
Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations. ISCA (1986)
Kei Hiraki, Kenji Nishida, Toshio Shimada
Evaluation of Associative Memory Using Parallel Chained Hashing. IEEE Trans. Computers 33 (9) (1984)
Toshio Shimada, Kei Hiraki, Kenji Nishida
An Architecture of a Data Flow Machine and Its Evaluation. COMPCON (1984)
Toshitsugu Yuba, Yoshinori Yamaguchi, Toshio Shimada
A Control Mechanism of a Lisp-Based Data-Driven Machine. Inf. Process. Lett. 16 (3) (1983)