Login / Signup

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism.

Hajime KubosawaNaoshi HigakiSatoshi AndoHiromasa TakahashiYoshimi AsadaHideaki AnbutsuTomio SatoMasato SakateAtsuhiro SugaMichihide KimuraHideo MiyakeHiroshi OkanoAkira AsatoYasunori KimuraHiroshi NakayamaMasayoshi KimotoKatsuji HirochiHideki SaitoNorio KaidoYukihiro NakagawaToshio Shimada
Published in: IEEE J. Solid State Circuits (1999)
Keyphrases