FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design.
Nobuho HashimotoShinya Takamaeda-YamazakiPublished in: CoRR (2022)
Keyphrases
- depth estimation
- hw sw
- hardware software partitioning
- dynamic scenes
- hardware software
- stereo vision
- depth map
- embedded systems
- field programmable gate array
- video sequences
- stereo matching
- design methodology
- video frames
- video data
- depth information
- stereo pair
- real scenes
- real time
- space time
- multi view
- scene understanding
- low cost
- high quality
- disparity map
- hardware implementation
- feature matching
- image sequences
- video surveillance
- specular reflection
- vision system
- optical flow
- object recognition
- three dimensional
- image processing