Naoki Fujieda

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 19

Top Topics

Evaluation Framework

Random Number Generator

Fingerprint Authentication

Top Venues

CANDAR (Workshops)

IEICE Trans. Inf. Syst.

Int. J. Netw. Comput.

Publications

Naoki Fujieda, Atsuki Okuchi
A Novel Remote FPGA Lab Platform Using MCU-based Controller Board. TALE (2023)
Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe
Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator. IEICE Trans. Inf. Syst. 106 (12) (2023)
Ryusei Oya, Naoki Fujieda, Shuichi Ichikawa
An HLS implementation of on-the-fly randomness test for TRNGs. CANDAR (2022)
Naoki Fujieda
A Python-based evaluation framework for stochastic computing circuits on FPGA SoC. CANDAR (Workshops) (2021)
Naoki Fujieda, Sogo Takashima
An MMCM-based high-speed true random number generator for Xilinx FPGA. Int. J. Netw. Comput. 11 (2) (2021)
Shunsuke Matsuoka, Shuichi Ichikawa, Naoki Fujieda
A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC). Int. J. Circuit Theory Appl. 49 (10) (2021)
Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa
An Analysis of DCM-Based True Random Number Generator. IEEE Trans. Circuits Syst. II Express Briefs (6) (2020)
Naoki Fujieda
On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs. FPL (2020)
Naoki Fujieda, Sogo Takashima
Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator. CANDAR (Workshops) (2020)
Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa
A light-weight implementation of latch-based true random number generator. IWCMC (2019)
Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files. IEICE Trans. Inf. Syst. (6) (2018)
Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa
A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity. TENCON (2018)
Naoki Fujieda, Shuichi Ichikawa
A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs. IEICE Electron. Express 15 (10) (2018)
Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa
An Analysis on Randomness of Path ORAM for Light-Weight Implementation. CANDAR Workshops (2018)
Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa
A Virtual Cache for Overlapped Memory Accesses of Path ORAM. Int. J. Netw. Comput. 7 (2) (2017)
Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka
Evaluation of the hardwired sequence control system generated by high-level synthesis. ISIE (2017)
Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa
An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis. CANDAR (2017)
Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa
Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM. CANDAR (2016)
Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa
Design and implementation of instruction indirection for embedded software obfuscation. Microprocess. Microsystems 45 (2016)
Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa
A Complement to Enhanced Instruction Register File against Embedded Software Falsification. PPREW@ACSAC (2015)
Naoki Fujieda, Shuichi Ichikawa
An XOR-Based Approach to Merging Entries for Instruction Register Files. CANDAR (2013)
Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. ARC (2012)
Naoki Fujieda, Kenji Kise
A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors. ICNC (2011)
Mochamad Asri, Naoki Fujieda, Kenji Kise
Rethinking processor instruction fetch: Inefficiencies-cracking mechanism. ISOCC (2011)