On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs.
Naoki FujiedaPublished in: FPL (2020)
Keyphrases
- random number generator
- field programmable gate array
- random number
- hardware implementation
- fpga implementation
- high speed
- embedded systems
- hardware design
- shift register
- hardware architecture
- image processing algorithms
- parallel computing
- fingerprint authentication
- computing systems
- general purpose
- image sequences
- information systems
- computer vision
- fpga technology
- real time