Shuichi Ichikawa

Publication Activity (10 Years)

Years Active: 1989-2023
Publications (10 Years): 17

Top Topics

Integer Arithmetic

High Level Synthesis

Top Venues

IEICE Trans. Inf. Syst.

IEICE Electron. Express

Publications

Shuichi Ichikawa
Pseudo-Random Number Generation by Staggered Sampling of LFSR. candar (2023)
Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe
Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator. IEICE Trans. Inf. Syst. 106 (12) (2023)
Ryusei Oya, Naoki Fujieda, Shuichi Ichikawa
An HLS implementation of on-the-fly randomness test for TRNGs. CANDAR (2022)
Shunsuke Matsuoka, Shuichi Ichikawa, Naoki Fujieda
A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC). Int. J. Circuit Theory Appl. 49 (10) (2021)
Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa
An Analysis of DCM-Based True Random Number Generator. IEEE Trans. Circuits Syst. II Express Briefs (6) (2020)
Shotaro Yamada, Shuichi Ichikawa
Netlist-based Measures for Hardware Obfuscation: A Preliminary Study. CANDAR (Workshops) (2020)
Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa
A light-weight implementation of latch-based true random number generator. IWCMC (2019)
Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files. IEICE Trans. Inf. Syst. (6) (2018)
Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa
A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity. TENCON (2018)
Naoki Fujieda, Shuichi Ichikawa
A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs. IEICE Electron. Express 15 (10) (2018)
Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa
An Analysis on Randomness of Path ORAM for Light-Weight Implementation. CANDAR Workshops (2018)
Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa
A Virtual Cache for Overlapped Memory Accesses of Path ORAM. Int. J. Netw. Comput. 7 (2) (2017)
Seiya Ogido, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa
A Study of a Fault-Tolerant System Using Dynamic Partial Reconfiguration. CANDAR (2017)
Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka
Evaluation of the hardwired sequence control system generated by high-level synthesis. ISIE (2017)
Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa
An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis. CANDAR (2017)
Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa
Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM. CANDAR (2016)
Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa
Design and implementation of instruction indirection for embedded software obfuscation. Microprocess. Microsystems 45 (2016)
Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa
A Complement to Enhanced Instruction Register File against Embedded Software Falsification. PPREW@ACSAC (2015)
Naoki Fujieda, Shuichi Ichikawa
An XOR-Based Approach to Merging Entries for Instruction Register Files. CANDAR (2013)
Hisashi Hata, Shuichi Ichikawa
FPGA Implementation of Metastability-Based True Random Number Generator. IEICE Trans. Inf. Syst. (2) (2012)
Satoru Tamura, Chikatoshi Yamada, Shuichi Ichikawa
Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning. ICNC (2012)
Shunsuke Matsuoka, Shuichi Ichikawa
Reduction of Power Consumption in Key-specific AES Circuits. ICNC (2012)
Shuichi Ichikawa
Foreword. IEICE Trans. Inf. Syst. (12) (2011)
Shuichi Ichikawa, Sho Takahashi, Yuu Kawai
Optimizing process allocation of parallel programs for heterogeneous clusters. Concurr. Comput. Pract. Exp. 21 (4) (2009)
Shuichi Ichikawa, Shoichiro Takagi
Estimating the Optimal Configuration of a Multi-Core Cluster: A Preliminary Study. CISIS (2009)
Shuichi Ichikawa, Takashi Sawada, Hisashi Hata
Diversification of Processors Based on Redundancy in Instruction Set. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Kazuhiro Hattanda, Shuichi Ichikawa
Redundancy in Instruction Sequences of Computer Programs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2006)
Ryoichiro Atono, Shuichi Ichikawa
Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm. IEICE Trans. Inf. Syst. (7) (2006)
Yoshinori Kishimoto, Shuichi Ichikawa
Optimizing the configuration of a heterogeneous cluster with multiprocessing and execution-time estimation. Parallel Comput. 31 (7) (2005)
Shiro Konuma, Shuichi Ichikawa
Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937. IEICE Trans. Inf. Syst. (12) (2005)
Yoshinori Kishimoto, Shuichi Ichikawa
An Execution-Time Estimation Model for Heterogeneous Clusters. IPDPS (2004)
Kazuhiro Hattanda, Shuichi Ichikawa
The Evaluation of Davidson's Digital Signature Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2004)
Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto
The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem. IEICE Trans. Inf. Syst. (8) (2004)
Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto
Data Dependent Circuit Design: A Case Study. FPL (2003)
Shuichi Ichikawa, H. Chiyama, K. Akabane
Redundancy in 3D Polygon Models and Its Application to Digital Signature. WSCG (2002)
Shuichi Ichikawa, Shoji Yamamoto
Data Dependent Circuit for Subgraph Isomorphism Problem. FPL (2002)
Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi
Hardware Accelerator for Subgraph Isomorphism Problems. FCCM (2000)
Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem. FPL (2000)
Shuichi Ichikawa, Mitsuhisa Sato, Eiichi Goto
Evaluation of range-checking addressing modes and the architecture of FLATS2. Systems and Computers in Japan 23 (10) (1992)
Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa
Pseudorandom Rounding for Truncated Multipliers. IEEE Trans. Computers 40 (9) (1991)
Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto
Multiple instruction streams in a highly pipelined processor. SPDP (1990)
Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto
Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking. ISCA (1989)
Kentaro Shimizu, Eiichi Goto, Shuichi Ichikawa
CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines. IEEE Trans. Computers 38 (6) (1989)