On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA.
Haruyoshi YonekawaHiroki NakaharaPublished in: IPDPS Workshops (2017)
Keyphrases
- neural network
- high speed
- single chip
- deep learning
- low cost
- network architecture
- programmable logic
- fermentation process
- low power consumption
- back propagation
- artificial neural networks
- rbf network
- real time
- low power
- neural network model
- high density
- genetic algorithm
- reconfigurable hardware
- neural network is trained
- field programmable gate array
- preprocessing
- analog vlsi
- systolic array
- input image
- associative memory
- recurrent neural networks
- pattern recognition
- vlsi implementation
- deep belief networks
- fault diagnosis