Kenichi Ohhata

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 7

Top Topics

Improved Particle Swarm Optimization

Wireless Transmission

Top Venues

IEICE Electron. Express

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yusuke Toyoshima, Ryosuke Kamiya, Kenichi Ohhata
High-Precision Open-Loop Time Amplifier Using Current Regulator. APCCAS (2023)
Daiki Ogata, Ryosuke Kamiya, Yusuke Toyoshima, Kenichi Ohhata
A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging. APCCAS (2022)
Chiwen Cheng, Kenichi Ohhata
A PVT-Robust Closed-Loop Dynamic Amplifier Using Three-Stage Floating Inverter Amplifier. APCCAS (2021)
Kenichi Ohhata
A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC. IEEE J. Solid State Circuits 54 (7) (2019)
Kenichi Ohhata, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Kouki Ueno, Yuuki Sonoda, Kenichiro Muroya
A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Kenichi Ohhata
A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTC. VLSI Circuits (2018)
Kenichi Ohhata
Low-Power, High-Speed Time-Based Subranging ADCs. ISPACS (2018)
Wataru Yoshimura, Kenichi Ohhata
Automatic technique of distortion compensation in resistor ladder for high-speed and low-power ADC. IEICE Electron. Express 11 (11) (2014)
Kenichi Ohhata
1-GHz, 17.5-mW, 8-bit Subranging ADC Using Offset-Cancelling Charge-Steering Amplifier. IEICE Trans. Electron. (4) (2014)
Kenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto
Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization. ISIC (2014)
Kenichi Ohhata, Hiroki Date, Mai Arita
Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging Technique. IEICE Trans. Electron. (12) (2011)
Norio Chujo, Toshiaki Takai, Toshiki Sugawara, Yasunobu Matsuoka, Daichi Kawamura, Koichiro Adachi, Tsuneo Kawamata, Tsuneo Ohno, Kenichi Ohhata
A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2011)
Kenichi Ohhata, Hironori Imamura, Toshinobu Ohno, Takaya Taniguchi, Kiichi Yamashita, Toru Yazaki, Norio Chujo
17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection. ISCAS (2010)
Norio Chujo, Tsuneo Kawamata, Kenichi Ohhata, Toshinobu Ohno
A 25Gb/s laser diode driver with mutually coupled peaking inductors for optical interconnects. CICC (2010)
Kenichi Ohhata, Koki Uchino, Yuichiro Shimizu, Kosuke Oyama, Kiichi Yamashita
Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture. IEEE J. Solid State Circuits 44 (11) (2009)
Kenichi Ohhata, Yuichiro Shimizu, Kiichi Yamashita
Feedthrough reduction technique for track-and-hold circuit with body-bias control circuit. IEICE Electron. Express 5 (13) (2008)
Takuma Nishimoto, Kiichi Yamashita, Kenichi Ohhata
Sandwich Structure Type RF-MEMS Variable Capacitor with Low Voltage Controllability and Wide Tuning Range. IEICE Trans. Commun. (2) (2008)
Kenichi Ohhata, Kosuke Yayama, Yuichiro Shimizu, Kiichi Yamashita
A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit. IEICE Electron. Express 4 (22) (2007)
Kenichi Ohhata, Katsuyoshi Harasawa, Makoto Honda, Kiichi Yamashita
Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology. IEICE Trans. Electron. (2) (2006)
Toru Masuda, Kenichi Ohhata, Nobuhiro Shiramizu, Eiji Ohue, Katsuya Oda, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Takashi Harada, Katsuyoshi Washio
SiGe-HBT-based 54-gb/s 4: 1 multiplexer IC with full-rate clock for serial communication systems. IEEE J. Solid State Circuits 40 (3) (2005)
Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. IEEE J. Solid State Circuits 35 (4) (2000)
Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. IEEE J. Solid State Circuits 35 (8) (2000)
Kenichi Ohhata, Toru Masuda, Kazuo Imai, Ryoji Takeyari, Katsuyoshi Washio
A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links. IEEE J. Solid State Circuits 34 (1) (1999)
Kenichi Ohhata, Toru Masuda, Eiji Ohue, Katsuyoshi Washio
Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamic range implemented in SiGe HBT. IEEE J. Solid State Circuits 34 (9) (1999)
Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. IEEE J. Solid State Circuits 31 (10) (1996)
Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. IEEE J. Solid State Circuits 30 (4) (1995)