Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology.
Kenichi OhhataKatsuyoshi HarasawaMakoto HondaKiichi YamashitaPublished in: IEICE Trans. Electron. (2006)
Keyphrases
- low power
- cmos technology
- low power consumption
- high speed
- power consumption
- single chip
- low cost
- power dissipation
- vlsi architecture
- mixed signal
- logic circuits
- digital signal processing
- low voltage
- gate array
- ultra low power
- parallel processing
- image sensor
- cmos image sensor
- nm technology
- design process
- design methodology
- power reduction