Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz.
Kenichi OhhataFumihiko ArakawaTakeshi KusunokiHiroaki NambuKazuo KanetaniKaname YamasakiKeiichi HigetaMasami UsamiMasahiko NishiyamaKunihiko YamaguchiNoriyuki HommaAtsuo HottaPublished in: IEEE J. Solid State Circuits (2000)