A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.
Keiichi HigetaMasami UsamiMasayuki OhayashiYasuhiro FujimuraMasahiko NishiyamaSatoru IsomuraKunihiko YamaguchiYouji IdeiHiroaki NambuKenichi OhhataNadateru HantaPublished in: IEEE J. Solid State Circuits (1996)
Keyphrases
- random access memory
- circuit design
- low power
- logic circuits
- design considerations
- power consumption
- low voltage
- chip design
- cmos technology
- high speed
- low cost
- built in self test
- embedded dram
- analog vlsi
- single chip
- image sensor
- digital circuits
- network simulator
- nm technology
- wide dynamic range
- mixed signal
- artificial immune system
- power dissipation
- delay insensitive
- main memory
- anomaly detection
- power supply
- focal plane
- random access
- memory access
- flash memory
- data transmission
- modal logic
- cmos image sensor
- physical design
- logic programming
- wireless sensor networks