FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture.
Masanori HariyamaYasuhiro KobayashiHaruka SasakiMichitaka KameyamaPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2005)
Keyphrases
- parallel architecture
- stereo matching
- fpga implementation
- hardware implementation
- depth discontinuities
- search range
- disparity range
- systolic array
- depth map
- stereo vision
- dense disparity map
- dynamic programming
- belief propagation
- stereo images
- efficient implementation
- stereo matching algorithm
- disparity map
- shared memory
- matching cost
- stereo correspondence
- parallel processing
- signal processing
- image processing algorithms
- field programmable gate array
- distributed memory
- parallel implementation
- processing elements
- stereo algorithm
- image matching
- stereo pair
- post processing
- higher order
- real time
- high quality
- pattern recognition
- image analysis
- motion estimation
- multi view