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Wire congestion aware synthesis for a dynamically reconfigurable processor.
Takao Toi
Takumi Okamoto
Toru Awashima
Kazutoshi Wakabayashi
Hideharu Amano
Published in:
FPT (2010)
Keyphrases
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parallel processing
texture synthesis
genetic algorithm
high speed
database systems
packet loss
computer architecture
single chip
congestion control
steady state
ip networks
traffic congestion
traffic volume