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Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU.
Kazutoshi Wakabayashi
Takashi Takenaka
Hiroaki Inoue
Published in:
ASP-DAC (2014)
Keyphrases
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high level synthesis
hardware implementation
parallel architecture
significant improvement
optimal solution
low cost
real time
artificial intelligence
high speed
information systems
computer science
hardware architecture
real world
computer vision
search space
parallel processing