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Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis.
Toshinobu Matsuba
Yuko Hara
Hiroyuki Tomiyama
Shinya Honda
Hiroaki Takada
Published in:
DELTA (2010)
Keyphrases
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high level synthesis
high speed
parallel architecture
image processing
image enhancement
power consumption
image analysis
design space exploration
bayesian networks