FPGA implementation technique for power consumption aware tamper resistance accelerator of lightweight PUF.
Yoshiya IkezakiYusuke NozakiHideki NagataMasaya YoshikawaPublished in: GCCE (2017)
Keyphrases
- lightweight
- power consumption
- fpga implementation
- field programmable gate array
- hardware implementation
- low power
- energy efficiency
- power saving
- embedded systems
- power management
- data center
- parallel implementation
- battery life
- energy saving
- parallel computing
- computing systems
- wireless sensor networks
- real time
- image processing algorithms
- transfer function
- authentication protocol
- computer vision
- power reduction