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Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption.

Masaya YoshikawaHidekazu Terai
Published in: J. Adv. Comput. Intell. Intell. Informatics (2007)
Keyphrases
  • low power consumption
  • genetic algorithm
  • low cost
  • low power
  • power consumption
  • real time
  • application specific
  • high speed
  • parallel processing
  • parallel implementation
  • massively parallel
  • field programmable gate array