Hidekazu Terai

Publication Activity (10 Years)

Years Active: 1983-2009
Publications (10 Years): 0

Publications

Masaya Yoshikawa, Hidekazu Terai
OX Hardware Engine for High Speed Character Inheritance. GEM (2009)
Masaya Yoshikawa, Hidekazu Terai
Dedicated Hardware for Ant Colony Optimization Using Distributed Memory. ITNG (2009)
Masaya Yoshikawa, Hidekazu Terai
Car Navigation System Based on Hybrid Genetic Algorithm. CSIE (5) (2009)
Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai
Hybrid Architecture of Genetic Algorithm and Simulated Annealing. Eng. Lett. 16 (3) (2008)
Masaya Yoshikawa, Hidekazu Terai
Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization. GEM (2008)
Masaya Yoshikawa, Hidekazu Terai
Route selection algorithm based on integer operation Ant Colony Optimization. IRI (2008)
Masaya Yoshikawa, Hidekazu Terai
The new DFM approach based on a genetic algorithm. Artif. Life Robotics 11 (1) (2007)
Masaya Yoshikawa, Hidekazu Terai
Architecture for high-speed Ant Colony Optimization. IRI (2007)
Masaya Yoshikawa, Hidekazu Terai
Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption. J. Adv. Comput. Intell. Intell. Informatics 11 (2) (2007)
Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai
Immune Algorithm Processor. CATA (2006)
Masaya Yoshikawa, Hidekazu Terai
Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. SERA (2006)
Masaya Yoshikawa, Hidekazu Terai
Co-evolutionary robotics using two kinds of neural networks. CAINE (2006)
Masaya Yoshikawa, Hidekazu Terai
Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation. J. Adv. Comput. Intell. Intell. Informatics 10 (1) (2006)
Masaya Yoshikawa, Hidekazu Terai
Hybrid genetic algorithm engine for high-speed floorplanning. ECCTD (2005)
Masaya Yoshikawa, Hidekazu Terai
Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. SERA (2005)
Masaya Yoshikawa, Hidekazu Terai
Performance driven placement technique based on collaboration of software and hardware. Congress on Evolutionary Computation (2005)
Masaya Yoshikawa, Hidekazu Terai
A Hierarchical Parallel Placement Technique based on Genetic Algorithm. ISDA (2005)
Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi
VLSI processor architecture for real-time GA processing and PE-VLSI design. ISCAS (3) (2004)
Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi
Scalable GA processor architecture and its implementation of processor-element. ICASSP (2002)
Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno
Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1. DAC (1994)
Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto
Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers. DAC (1991)
Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa
Automatic Layout Procedures for Serial Routing Devices. DAC (1988)
Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs. DAC (1986)
Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa
A routing procedure for mixed array of custom macros and standard cells. DAC (1985)
Tokinori Kozawa, Hidekazu Terai
Research in Design Automation for VLSI Layout. IEEE Des. Test 2 (5) (1985)
Tokinori Kozawa, Chihei Miura, Hidekazu Terai
Combine and top down block placement algorithm for hierarchical logic VLSI layout. DAC (1984)
Tokinori Kozawa, Hidekazu Terai, Tatsuki Ishii, Michiyoshi Hayase, Chihei Miura, Yasushi Ogawa, Kuniaki Kishida, Norio Yamada, Yasuhiro Ohno
Automatic placement algorithms for high packing density V L S I. DAC (1983)