Kazuhito Ito

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 10

Top Topics

Multiscale Representation

Energy Minimization

Error Detection

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Proc. Meet. Acoust.

IEICE Electron. Express

Publications

Yuya Kitazawa, Kazuhito Ito
Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Yuki Imai, Shinichi Nishizawa, Kazuhito Ito
Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Kazuhito Ito
Energy Minimization of Double Modular Redundant Conditional Processing by Common Condition Dependency. IEICE Trans. Electron. (4) (2020)
Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito
Analog circuit design methodology utilizing a structure of thin BOX FDSOI. IEICE Electron. Express 16 (5) (2019)
Seiji Nakagawa, Kazuhito Ito
Mechanisms of Bone-conducted Ultrasonic Perception Assessed by Measurements of Acoustic Fields in the Outer Ear Canal and Vibrations of the Tympanic Membrane. EMBC (2018)
Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa
Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Shunsuke Tamura, Miduki Mori, Kazuhito Ito, Nobuyuki Hirose, Shuji Mori
Study on interactions between voicing production and perception using auditory feedback paradigm. Proc. Meet. Acoust. 31 (1) (2017)
Kazuhito Ito
Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Seiji Nakagawa, Takuya Hotehama, Kazuhito Ito, Tomohiro Inagaki
Development of bone-conduction mobile phones: Assessment of hearing mechanisms by measuring psychological characteristics and acoustical properties in the outer ear canal. EMBC (2016)
Kazuhito Ito, Hiroki Hayashi
Hardware-Efficient Local Extrema Detection for Scale-Space Extrema Detection in SIFT Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Kazuhito Ito
A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2015)
Kazuhito Ito
Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Kazuhito Ito
An Area-Time Efficient Key Equation Solver with Euclidean Algorithm for Reed-Solomon Decoders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2013)
Kazuhito Ito, Ryoto Shirasaka
Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Kazuhito Ito, Kazuhiko Kameda
A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Kazuhito Ito, Takuya Numata
Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors. IEICE Trans. Electron. (4) (2013)
Kazuhito Ito, Kazuhiko Kameda
A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities. Inf. Media Technol. 8 (2) (2013)
Kazuhito Ito, Keisuke Nasu
A Processor Accelerator for Software Decoding of Reed-Solomon Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2012)
Kazuhito Ito
Convolutional Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2012)
Hidekazu Seto, Kazuhito Ito
A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Kazuhito Ito
A Processor Accelerator for Software Decoding of BCH Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2010)
Kazuhito Ito, Hidekazu Seto
Reducing Power Dissipation of Data Communications on LSI with Scheduling Exploration. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Masayuki Masuda, Kazuhito Ito
Rapid and precise instruction set evaluation for application specific processor design. ISCAS (6) (2005)
Kazuhito Ito, Daisuke Suzuki
A high-level synthesis method for simultaneous placement and scheduling considering data communication delay. APCCAS (1) (2002)
Trio Adiono, Tsuyoshi Isshiki, Chawalit Honsawek, Kazuhito Ito, Dongju Li, Hiroaki Kunieda
New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2002)
Tsuyoshi Isshiki, Chawalit Honsawek, Trio Adiono, Kazuhito Ito, Tomohiko Ohtsuka, Dongju Li, Hiroaki Kunieda
H.263+ Video Encoder/Decoder LSI Featuring System-MSPA Architecture and Improved Rate Control Method. ISAS-SCI (1) (2001)
Kazuhito Ito
A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration. ASP-DAC (2000)
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
ILP-based cost-optimal DSP synthesis with module selection and data format conversion. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Kazuhito Ito, Keshab K. Parhi
A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis. J. VLSI Signal Process. 16 (1) (1997)
Kazuhito Ito, Takenobu Shimizugashira, Hiroaki Kunieda
High speed bit-serial parallel processing on array architecture. ASP-DAC (1997)
Kazuhito Ito, Keshab K. Parhi
Determining the minimum iteration period of an algorithm. J. VLSI Signal Process. 11 (3) (1995)
Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito
Automatic design for bit-serial MSPA architecture. ASP-DAC (1995)
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
Module selection and data format conversion for cost-optimal DSP synthesis. ICCAD (1994)