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Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics.
Takumi Egawa
Tohru Ishihara
Hidetoshi Onodera
Akihiko Shinya
Shota Kita
Kengo Nozaki
Kenta Takata
Masaya Notomi
Published in:
ICRC (2018)
Keyphrases
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logic circuits
nano scale
low power
optimization algorithm
optimization problems
gate array
pattern recognition
logic synthesis
enabling technologies
tunnel diode
neural network
high speed
input output
power consumption
end to end