Scalable Hardware Architecture for fast Gradient Boosted Tree Training.
Tamon SadasueTakuya TanakaRyosuke KasaharaArief DarmawanTsuyoshi IsshikiPublished in: IPSJ Trans. Syst. LSI Des. Methodol. (2021)
Keyphrases
- hardware architecture
- hardware implementation
- tree structure
- hardware architectures
- edge detection
- low cost
- boosted classifiers
- field programmable gate array
- training set
- case study
- software engineering
- general purpose
- real time
- signal processing
- index structure
- pattern recognition
- video sequences
- image processing
- computer vision
- artificial intelligence