Yasuhiro Takahashi

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 49

Top Topics

Quantum Computation

Optical Networks

Top Venues

IEICE Electron. Express

Publications

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. IEEE Trans. Circuits Syst. II Express Briefs 71 (5) (2024)
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. Microelectron. J. 145 (2024)
Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC (2024)
Koji Tominaga, Yasuhiro Takahashi
Low-Power, 25-Gb/s Active Voltage Current Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC (2024)
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. ICECS (2023)
Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. ASICON (2023)
Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. IEICE Electron. Express 20 (14) (2023)
Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. ISOCC (2023)
Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. IEICE Electron. Express 20 (18) (2023)
Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. ICEIC (2022)
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. MWSCAS (2022)
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. ICECS 2022 (2022)
Yuki Takeuchi, Yasuhiro Takahashi, Tomoyuki Morimae, Seiichiro Tani
Divide-and-conquer verification method for noisy intermediate-scale quantum computation. Quantum 6 (2022)
Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. MWSCAS (2022)
Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani
Classically simulating quantum circuits with local depolarizing noise. Theor. Comput. Sci. 893 (2021)
Câncio Monteiro, Yasuhiro Takahashi
Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices. Sensors 21 (24) (2021)
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. ICECS (2021)
Yasuhiro Takahashi, Seiichiro Tani
Power of uninitialized qubits in shallow quantum circuits. Theor. Comput. Sci. 851 (2021)
Kohei Ogura, Yasuhiro Takahashi
Special Session: An Adiabatic Logic Based Silicon Physical Unclonable Function. ICCD (2020)
Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani
Classically Simulating Quantum Circuits with Local Depolarizing Noise. MFCS (2020)
Yuki Takeuchi, Yasuhiro Takahashi, Seiichiro Tani
Efficiently generating ground states is hard for postselected quantum computation. CoRR (2020)
Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani
Classically Simulating Quantum Circuits with Local Depolarizing Noise. CoRR (2020)
Yasuhiro Takahashi, Hiroki Koyasu, S. Dinesh Kumar, Himanshu Thapliyal
Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function. SN Comput. Sci. 1 (5) (2020)
Hiroki Koyasu, Yasuhiro Takahashi
Performance and Security Evaluation of S-Box Using Current-Pass Optimized Symmetric Pass Gate Adiabatic Logic. SN Comput. Sci. 1 (4) (2020)
Yasuhiro Takahashi, Tosiron Adegbija, Linga Reddy Cenkeramaddi
Message from the Technical Program Chairs iSES 2020. iSES (2020)
Hiroki Koyasu, Yasuhiro Takahashi
Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 12 (2019)
Hiroki Koyasu, Yasuhiro Takahashi
Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic. ISVLSI (2019)
Yasuhiro Takahashi, Hiroki Koyasu, S. Dinesh Kumar, Himanshu Thapliyal
Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. ISVLSI (2019)
Mei Han, Yasuhiro Takahashi, Toshikazu Sekine
Non-floating and low-power adiabatic logic circuit. IEICE Electron. Express 16 (17) (2019)
Xiangyu Chen, Yasuhiro Takahashi
Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor. ISVLSI (2019)
Ryo Tagawa, Yasuhiro Takahashi
5.3 GHz, 69.6 dBΩ Transimpedance Amplifier with Negative Impedance Converter. ISPACS (2018)
Takumi Fukuura, Yasuhiro Takahashi
5.6 GHz, 61.7 dBΩ Transimpedance Amplifier Using Active Inductor in Shunt and Series Peaking Techniques. ISPACS (2018)
Ryosuke Ohashi, Yasuhiro Takahashi
A New Adiabatic Logic without Charge Sharing Gate for Cryptographic Devices. ISPACS (2018)
Yasuhiro Takahashi, Seiichiro Tani
Power of Uninitialized Qubits in Shallow Quantum Circuits. STACS (2018)
Câncio Monteiro, Apolinario Maria, Yasuhiro Takahashi
Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices. ISPACS (2018)
Yuya Kojima, Toshikazu Sekine, Yasuhiro Takahashi
Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture. ECCTD (2017)
Yasuhiro Takahashi, Toshikazu Sekine, Mei Han
Operational amplifier based LC resonant circuit for adiabatic logic. MIXDES (2017)
Mei Han, Yasuhiro Takahashi, Toshikazu Sekine
Low power Adiabatic Logic based on 2PC2AL. ICICDT (2017)
Yuki Takeuchi, Yasuhiro Takahashi
Ancilla-driven instantaneous quantum polynomial time circuit for quantum supremacy. CoRR (2016)
Yasuhiro Takahashi, Seiichiro Tani, Takeshi Yamazaki, Kazuyuki Tanaka
Commuting quantum circuits with few outputs are unlikely to be classically simulatable. Quantum Inf. Comput. 16 (3&4) (2016)
Yasuhiro Takahashi, Seiichiro Tani
Collapse of the Hierarchy of Constant-Depth Exact Quantum Circuits. Comput. Complex. 25 (4) (2016)
Yasuhiro Takahashi, Seiichiro Tani
Shallow Quantum Circuits with Uninitialized Ancillary Qubits. CoRR (2016)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. IET Circuits Devices Syst. 9 (5) (2015)
Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
An improved estimation method of 4 port S-parameters with 2 port measurements. ECCTD (2015)
Yasuhiro Takahashi, Seiichiro Tani, Takeshi Yamazaki, Kazuyuki Tanaka
Commuting Quantum Circuits with Few Outputs are Unlikely to be Classically Simulatable. COCOON (2015)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. NEWCAS (2015)
Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
SPICE model of memristive device using Tukey window function. IEICE Electron. Express 12 (5) (2015)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
Two phase clocked subthreshold adiabatic logic circuit. IEICE Electron. Express 12 (20) (2015)
Rui Manuel de Oliveira Amaral Sarmento, Yasuhiro Takahashi
Power saving analysis of step-down buck converter using adiabatic switching principle. ISPACS (2015)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. APCCAS (2014)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. APCCAS (2014)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
) using secure charge-sharing symmetric adiabatic logic. ISCAS (2014)
Yasuhiro Takahashi, Seiichiro Tani, Takeshi Yamazaki, Kazuyuki Tanaka
Commuting Quantum Circuits with Few Outputs are Unlikely to be Classically Simulatable. CoRR (2014)
Yasuhiro Takahashi, Takeshi Yamazaki, Kazuyuki Tanaka
Hardness of classically simulating quantum circuits with unbounded Toffoli and fan-out gates. Quantum Inf. Comput. 14 (13-14) (2014)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Process variation verification of low-power secure CSSAL AES S-box circuit. MWSCAS (2014)
Haruki Ogata, Yasuhiro Takahashi, Toshikazu Sekine
Power dissipation analysis of memristor for low power integrated circuit applications. APCCAS (2014)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
Two phase clocking subthreshold adiabatic logic. ISCAS (2014)
Yasuhiro Takahashi, Seiichiro Tani
Collapse of the Hierarchy of Constant-Depth Exact Quantum Circuits. Computational Complexity Conference (2013)
Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
An estimation method for the 3 port S-parameters with 1 port measurements. ECCTD (2013)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
) in 0.18μm CMOS technology. ECCTD (2013)
Thomas Hobiger, Yasuhiro Takahashi, Maho Nakamura, Tadahiro Gotoh, Shinichi Hama, Takashi Maruyama, Tsutomu Nagatsuma, Hiroyuki Noda, Motohisa Kishimoto, Kaoru Nakayama, Yasuhiro Ohki
Dissemination of UTC(NICT) by Means of QZSS. IEEE Trans. Instrum. Meas. 62 (6) (2013)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
DPA resistance of charge-sharing symmetric adiabatic logic. ISCAS (2013)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. Microelectron. J. 44 (6) (2013)
Yasuhiro Takahashi, Takeshi Yamazaki, Kazuyuki Tanaka
Hardness of Classically Simulating Quantum Circuits with Unbounded Toffoli and Fan-Out Gates. MFCS (2013)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. TSP (2013)
Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama
Power-saving analysis of adiabatic logic in subthreshold region. ISPACS (2012)
Yasuhiro Takahashi, Zhongyu Luo, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama
2PCDAL: Two-phase clocking dual-rail adiabatic logic. APCCAS (2012)
Yuki Urata, Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan
A low-power sense amplifier for adiabatic memory using memristor. APCCAS (2012)
Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine
LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron. J. 43 (4) (2012)
Yasuhiro Takahashi, Akinori Maeda, Mitsuhiro Ogura
Actual implementation of multi domain test: Further reduction of cost of test. ITC (2011)
Yasuhiro Takahashi, Akinori Maeda
Multi Domain Test: Novel test strategy to reduce the Cost of Test. VTS (2011)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. ISPACS (2011)
Hides Jamima, Yasuhiro Takahashi, Toshikazu Sekine
Low-power adiabatic SRAM. ISPACS (2011)
Yasuhiro Takahashi, Seiichiro Tani
Constant-Depth Exact Quantum Circuits for the OR and Threshold Functions CoRR (2011)
Yasuhiro Takahashi
Simple Sets of Measurements for Universal Quantum Computation and Graph State Preparation. TQC (2010)
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. VLSI-SoC (2010)
Yasuhiro Takahashi, Seiichiro Tani, Noboru Kunihiro
Quantum addition circuits and unbounded fan-out. Quantum Inf. Comput. 10 (9&10) (2010)
Yasuhiro Takahashi
Quantum Arithmetic Circuits: A Survey. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2009)
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. ECCTD (2009)
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
Two phase clocked adiabatic static CMOS logic. SoC (2009)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. ICECS (2009)
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
Fundamental logics based on two phase clocked adiabatic static CMOS logic. ICECS (2009)
Yasuhiro Takahashi, Noboru Kunihiro
A fast quantum circuit for addition with few qubits. Quantum Inf. Comput. 8 (6) (2008)
Yasuhiro Takahashi, Noboru Kunihiro, Kazuo Ohta
The quantum fourier transform on a linear nearest neighbor architecture. Quantum Inf. Comput. 7 (4) (2007)
Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic. IEICE Trans. Electron. (10) (2007)
Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2007)
Yasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic. APCCAS (2006)
Yasuhiro Takahashi, Noboru Kunihiro
A quantum circuit for shor's factoring algorithm using 2n + 2 qubits. Quantum Inf. Comput. 6 (2) (2006)
Yasuhiro Takahashi, Michio Yokoyama
New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination. ISCAS (2) (2005)
Yasuhiro Takahashi, Noboru Kunihiro
A linear-size quantum circuit for addition with no ancillary qubits. Quantum Inf. Comput. 5 (6) (2005)
Yasuhiro Takahashi, Kei-ichi Konta, Kazukiyo Takahashi, Michio Yokoyama, Kazuhiro Shouno, Mitsuru Mizunuma
Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2003)
Yasuhiro Takahashi, Yasuhito Kawano, Masahiro Kitagawa
On the computational power of constant-depth quantum circuits with gates for addition. IEEE Congress on Evolutionary Computation (2003)
Yasuhiro Takahashi, Kohji Dohsaka, Kiyoaki Aikawa
An efficient dialogue control method using decision tree-based estimation of out-of-vocabulary word attributes. INTERSPEECH (2002)
Tohru Hoshi, Kenjiro Mori, Yasuhiro Takahashi, Yoshiyuki Nakayama, Takeshi Ishizaki
B-ISDN Multimedia Communication and Collaboration Platform Using Advanced Video Workstations to Support Cooperative Work. IEEE J. Sel. Areas Commun. 10 (9) (1992)
Tohru Hoshi, Yasuhiro Takahashi, Kenjiro Mori
An integrated multimedia desktop communication and collaboration platform for broadband ISDN: the broadband ISDN group tele-working system. Comput. Commun. Rev. 22 (3) (1992)