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VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic.

Yasuhiro TakahashiToshikazu SekineMichio Yokoyama
Published in: IEICE Trans. Electron. (2007)
Keyphrases
  • vlsi implementation
  • random access memory
  • vlsi architecture
  • low cost
  • real time
  • image data
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  • delay insensitive
  • pattern recognition
  • image enhancement
  • data compression
  • floating point
  • fir filters