Toshikazu Sekine

Publication Activity (10 Years)

Years Active: 2006-2019
Publications (10 Years): 9

Top Topics

Cmos Technology

Delay Insensitive

Top Venues

IEICE Electron. Express

Publications

Mei Han, Yasuhiro Takahashi, Toshikazu Sekine
Non-floating and low-power adiabatic logic circuit. IEICE Electron. Express 16 (17) (2019)
Yuya Kojima, Toshikazu Sekine, Yasuhiro Takahashi
Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture. ECCTD (2017)
Yasuhiro Takahashi, Toshikazu Sekine, Mei Han
Operational amplifier based LC resonant circuit for adiabatic logic. MIXDES (2017)
Mei Han, Yasuhiro Takahashi, Toshikazu Sekine
Low power Adiabatic Logic based on 2PC2AL. ICICDT (2017)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. IET Circuits Devices Syst. 9 (5) (2015)
Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
An improved estimation method of 4 port S-parameters with 2 port measurements. ECCTD (2015)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. NEWCAS (2015)
Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
SPICE model of memristive device using Tukey window function. IEICE Electron. Express 12 (5) (2015)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
Two phase clocked subthreshold adiabatic logic circuit. IEICE Electron. Express 12 (20) (2015)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. APCCAS (2014)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. APCCAS (2014)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
) using secure charge-sharing symmetric adiabatic logic. ISCAS (2014)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Process variation verification of low-power secure CSSAL AES S-box circuit. MWSCAS (2014)
Haruki Ogata, Yasuhiro Takahashi, Toshikazu Sekine
Power dissipation analysis of memristor for low power integrated circuit applications. APCCAS (2014)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
Two phase clocking subthreshold adiabatic logic. ISCAS (2014)
Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
An estimation method for the 3 port S-parameters with 1 port measurements. ECCTD (2013)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
) in 0.18μm CMOS technology. ECCTD (2013)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
DPA resistance of charge-sharing symmetric adiabatic logic. ISCAS (2013)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. Microelectron. J. 44 (6) (2013)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. TSP (2013)
Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama
Power-saving analysis of adiabatic logic in subthreshold region. ISPACS (2012)
Yasuhiro Takahashi, Zhongyu Luo, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama
2PCDAL: Two-phase clocking dual-rail adiabatic logic. APCCAS (2012)
Yuki Urata, Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan
A low-power sense amplifier for adiabatic memory using memristor. APCCAS (2012)
Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine
LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron. J. 43 (4) (2012)
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine
Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. ISPACS (2011)
Hides Jamima, Yasuhiro Takahashi, Toshikazu Sekine
Low-power adiabatic SRAM. ISPACS (2011)
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. VLSI-SoC (2010)
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. ECCTD (2009)
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
Two phase clocked adiabatic static CMOS logic. SoC (2009)
Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine
A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. ICECS (2009)
Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine
Fundamental logics based on two phase clocked adiabatic static CMOS logic. ICECS (2009)
Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic. IEICE Trans. Electron. (10) (2007)
Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama
A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2007)
Yasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic. APCCAS (2006)