LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier.
Nazrul Anuar NayanYasuhiro TakahashiToshikazu SekinePublished in: Microelectron. J. (2012)
Keyphrases
- low power
- cmos technology
- power consumption
- analog to digital converter
- random access memory
- low cost
- high speed
- logic circuits
- low voltage
- image sensor
- vlsi architecture
- delay insensitive
- ultra low power
- single chip
- mixed signal
- vlsi circuits
- gate array
- high power
- design considerations
- signal processor
- digital signal processing
- hardware implementation
- wireless transmission
- flip flops
- nm technology
- latent semantic indexing
- floating point
- low power consumption
- focal plane
- wide dynamic range
- image processing