4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR.

Nazrul Anuar Yasuhiro Takahashi Toshikazu Sekine

Published in: VLSI-SoC (2010)

Keyphrases

random access memory
design considerations
low voltage
low power
hardware implementation
floating point
image sensor
analog to digital converter
image processing
logic programming
parallel processing
classical logic
memory access
type ii
logical operations