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A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic.

Kazunari KatoYasuhiro TakahashiToshikazu Sekine
Published in: NEWCAS (2015)
Keyphrases
  • circuit design
  • bit parallel
  • logic programs
  • hardware implementation
  • floating point
  • latent semantic indexing
  • logical operations
  • clustering algorithm
  • logic programming
  • text retrieval
  • efficient implementation