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Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process.
Yasuhiro Takahashi
Daisuke Ito
Makoto Nakamura
Akira Tsuchiya
Toshiyuki Inoue
Keiji Kishine
Published in:
IEICE Electron. Express (2023)
Keyphrases
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low power
high speed
high power
power consumption
cmos technology
low cost
single chip
digital signal processing
vlsi circuits
power reduction
nm technology
wireless transmission
real time
low power consumption
image sensor
wireless networks
vlsi architecture
logic circuits
mixed signal