A Low-Power Reconfigurable DNN Accelerator for Instruction-Extended RISC-V.
Hansen WangDongju LiTsuyoshi IsshikiPublished in: IPSJ Trans. Syst. LSI Des. Methodol. (2024)
Keyphrases
- low power
- low cost
- low power consumption
- field programmable gate array
- power consumption
- high speed
- instruction set
- power reduction
- single chip
- high power
- general purpose
- wireless transmission
- application specific
- embedded systems
- vlsi circuits
- digital signal processing
- vlsi architecture
- hardware implementation
- real time
- image processing algorithms
- parallel computing
- cmos technology
- hardware and software
- parallel implementation
- image sensor
- computing systems
- compute intensive
- gate array