Login / Signup
Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA.
Seiya Shirakuni
Ittetsu Taniguchi
Hiroyuki Tomiyama
Published in:
IPSJ Trans. Syst. LSI Des. Methodol. (2019)
Keyphrases
</>
high speed
data sets
low cost
design process
formative evaluation
bayesian decision problems
verilog hdl
image processing
case study
learning environment
signal processing
building blocks
decision problems
design principles
integrated circuit
assessment tool