A Compression Router for Low-Latency Network-on-Chip.

Naoya Niwa Yoshiya Shikama Hideharu Amano Michihiro Koibuchi

Published in: IEICE Trans. Inf. Syst. (2023)

Keyphrases

network on chip
low latency
high speed
high throughput
routing algorithm
highly efficient
real time
virtual machine
network simulator
multi processor
stream processing
data transfer
data analysis
low complexity
ad hoc networks
power dissipation