Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.
Yoshiki SaitoTomoaki ShiraiTakuro NakamuraTakashi NishimuraYohei HasegawaSatoshi TsutsumiToshihiro KashimaMitsutaka NakataSeidai TakedaKimiyoshi UsamiHideharu AmanoPublished in: FPT (2008)