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Power reduction techniques for Dynamically Reconfigurable Processor Arrays.
Takashi Nishimura
Keiichiro Hirai
Yoshiki Saito
Takuro Nakamura
Yohei Hasegawa
Satoshi Tsutsumi
Vasutan Tunbunheng
Hideharu Amano
Published in:
FPL (2008)
Keyphrases
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power reduction
power consumption
low power
multithreading
high speed
power saving
power dissipation
low cost
parallel processing
energy efficiency
image processing
computational power
parallel computing
coarse grained