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A low-power design method using multiple supply voltages.

Mutsunori IgarashiKimiyoshi UsamiKazutaka NogamiFumihiro MinamiYukio KawasakiTakahiro AokiMidori TakanoChiharo MizunoTakashi IshikawaMasahiro KanazawaShinji SonodaMakoto IchidaNaoyuki Hatanaka
Published in: ISLPED (1997)
Keyphrases
  • low power
  • single chip
  • computational complexity
  • high speed
  • power consumption
  • low cost
  • high power
  • low power consumption
  • low complexity
  • cmos technology
  • vlsi architecture