On-chip detection methodology for break-even time of power gated function units.
Kimiyoshi UsamiYuya GotoKensaku MatsunagaSatoshi KoyamaDaisuke IkebuchiHideharu AmanoHiroshi NakamuraPublished in: ISLPED (2011)
Keyphrases
- power consumption
- automatic detection
- low cost
- false alarms
- object detection
- high speed
- multithreading
- high density
- ibm power processor
- detection algorithm
- false positives
- neural network
- chip design
- detection method
- real time
- detection rate
- target detection
- single chip
- anomaly detection
- analog vlsi
- object recognition
- functional verification