A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme.
Mototsugu HamadaMasafumi TakahashiHideho ArakidaAkihiko ChibaToshihiro TerazawaTakashi IshikawaMasahiro KanazawaMutsunori IgarashiKimiyoshi UsamiTadahiro KurodaPublished in: CICC (1998)
Keyphrases
- low power
- power consumption
- low cost
- low power consumption
- single chip
- high speed
- logic circuits
- power dissipation
- digital signal processing
- vlsi architecture
- cmos technology
- power reduction
- mixed signal
- gate array
- design process
- wireless transmission
- real time
- low complexity
- power system
- signal processing
- energy dissipation