Clustered voltage scaling technique for low-power design.
Kimiyoshi UsamiMark HorowitzPublished in: ISLPD (1995)
Keyphrases
- low power
- single chip
- high speed
- power consumption
- low cost
- vlsi architecture
- low power consumption
- logic circuits
- cmos technology
- mixed signal
- gate array
- digital signal processing
- power dissipation
- wireless transmission
- design process
- vlsi circuits
- design methodology
- power reduction
- nm technology
- energy dissipation
- low voltage
- image sensor
- real time
- ultra low power
- high power
- motion estimation