Scalable deep neural network accelerator cores with cubic integration using through chip interface.
Ryuichi SakamotoRyo TakataJun IshiiMasaaki KondoHiroshi NakamuraTetsui OhkuboTakuya KojimaHideharu AmanoPublished in: ISOCC (2017)
Keyphrases
- neural network
- high speed
- back propagation
- low cost
- high density
- level parallelism
- artificial neural networks
- user interface
- graphical interface
- data integration
- neural network model
- processor core
- parallel implementation
- fault diagnosis
- fuzzy logic
- pattern recognition
- genetic algorithm
- user friendly
- multilayer perceptron
- b spline
- prediction model
- neural nets
- multi layer
- network architecture
- self organizing maps
- single chip
- modular design
- analog vlsi
- neural network is trained