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1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Yisuo LiKen'ichi KanazawaTetsuo IzawaKoji SakuiGeorg StrofOskar BaumgartnerGerhard RzepaMarkus KarnerZlatan StanojevicNozomu HaradaFujio Masuoka
Published in: IMW (2021)
Keyphrases
  • leakage current
  • cmos technology
  • low voltage
  • low power
  • software engineering
  • data sets
  • high speed
  • design process
  • power consumption
  • electrical properties